A read operation of information stored in a multi-level non-volatile memory cell is commonly carried out by applying a voltage ramp to the control gate for establishing the level at which the programmed multi-level cell enters a conduction state.
The voltage ramp applied to the control gate of an addressed array cell needs to be replicated with high precision on a reference cell. Naturally, substantially identical voltage ramps are respectively applied to the array wordline to which the addressed cell belongs, and to the wordline of a row of reference cells.
In the design of a multi-level FLASH memory device with voltage ramp reading, there is often a requirement to reduce in size the driver of the wordlines (WL) that is generally integrated adjacent to the array of memory cells.
Reading techniques based on applying a voltage ramp to the control gates of the cells require a close match between the voltage ramp that is applied on the reference wordline WLref and the voltage ramp that is applied on the array wordline WLarray, or at least a fair repeatability at all the operative corners. To this end, it is important to provide very good electrical connections of the wordline WL to be read, and of the wordline WL of the array of reference cells to the charge current source.
FIG. 1 shows a typical multi-sector partition of a non-volatile memory device. It also illustrates, in addition to the location of relevant components, the electrical parameters (capacitances) that play a fundamental role in generation of the read voltage ramp on the selected array wordline and reference wordline. The ramp generator Ramp Gen supplies a whole partition that will present a capacitive load composed of WLref+WLarray+Metal.
Referring now to FIG. 2, a comparison is made, only by way of example, of two possible architectures. In the architecture shown on the left side, the ramp generator RampGen sees a parasitic capacitance of the connection line Metal. This value is comparable to that of the two wordlines to be charged, WL array and WLref. In a situation such as that shown on the left side, it is accepted as a tolerable loss of charge the charging of the parasitic capacitance of the connection metal line.
In the architecture shown on the right side, where the banks of sense amplifiers are not replicated for the single partitions but are formed at one end of the array to serve all sectors, the bitlines (BL) tend to be particularly long by extending themselves through the whole array or partition thereof. As a consequence, the row decoding circuit RowDec that borders one side of the array is relatively long. In these devices, the parasitic capacitance of the connection line Metal may become larger than the capacitance of the two wordlines to be charged during a read phase.
Wasting such a large percentage of current for generating the read voltage ramp on the two selected wordlines WLarray and WLref is very penalizing. A relevant portion of the current absorbed for a read operation is wasted for charging the parasitic capacitance of the long metal line. The current for generating the read voltage ramp is generated from voltage boosted nodes, and thus, it is proportionally relevant on the total power dissipation and on the area of integration of the device.